ملاحظة: إعلان الوظيفة هذا انتهت صلاحيته.

Design and Verification Engineer

30/12/2019 |

وظيفة منشورة بالتعاون مع موقع פורטל דרושים

  تفاصيل الوظيفة

المحتوى بهذه الصفحة غير موجود باللغة التي اخترتها للتصفح.

Come join Marvell, our excellent team working on cutting-edge Intelligent Processors.
Drive the future of data processing for the Enterprise, Data Center, and Wireless Infrastructure applications.
Take the next step in your career. Learn and share your knowledge and expertise with others.
Feel excited to work with great colleagues, in a dynamic environment.
Invent, define, and implement.
As a Design and Verification Engineer, you will participate in all front-end phases of product development.
You will participate in Design (Definition, u-Architecture, RTL design and Debug) and/or Verification activities (UVM TB planning and coding, random testing and debugging)
Job Requirements:
• B.Sc. or above in Electronic Engineering or equivalent
• At least 3 years of experience in RTL design or verification
• Design RTL experience in Verilog/SV or verification experience in SV-UVM / e-UVM
• Good team work and collaboration skills

مكان الوظيفة: أي مكان
الشركة: Marvell

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